About Sintel
Sintel is a simulator and modeler for basic digital systems that allows, in addition to visualizing inputs and outputs in real time, to export the model to a hardware description language such as VHDL and verilog.
Sintel was born as a proposal for undergraduate work for the degree of Electronic Engineer at the Universidad del Quindío in Armenia Quindío.
Developed by Wilfer Daniel Ciro Maya with collaboration of Luis Miguel Capacho Valbuena.
Bugs report: https://gitlab.com/WilferCiro/sintel/issues
Documentation: https://sintel.readthedocs.io/en/latest/
Send a message to creators
